A semiconductor device typically includes a metal oxide semiconductor (MOS) transistor, which includes a gate stack. FIG. 1 illustrates a conventional gate stack including a gate electrode 110′, where the gate stack is on a semiconductor substrate 101. As shown in FIG. 1, the gate electrode 110′ is on a gate insulator 102, which is on the semiconductor substrate 101. A capping layer 121, typically containing silicon nitride, is on the gate electrode 110′. Also illustrated in FIG. 1, the gate electrode 110′ includes a metal layer 115′ (typically containing tungsten), on a refractory layer 114 (typically containing tungsten nitride), which is on a diffusion barrier layer 117 (typically containing titanium nitride). The diffusion barrier layer 117 is on a conductive layer 116 (typically containing titanium silicide), which is on a gate layer 112′ (typically containing polycrystalline silicon (poly)). The gate layer is implanted with ions, such as As+, to enhance conductivity of the gate layer, right after formation of the gate layer and before the formation of other layers on the gate layer.
A conventional MOS transistor 210 containing the conventional gate stack is illustrated in FIG. 2. As shown, the transistor includes gate spacers 208 on either side of the gate stack. The transistor also includes source/drain regions 221 and 222, as well as isolation regions 201 in the substrate. During processing, the gate electrode 110′ may loose nitrogen from the refractory layer 114, so that when the refractory layer contains tungsten nitride and the metal layer 115′ contains tungsten, the refractory layer will merge into the metal layer 115′. The conventional MOS transistor and gate stack is described, for example, in U.S. Pat. No. 6,902,993 to Blosse et al. issued 7 Jun. 2005.
As part of processing the gate stack to form the conventional MOS transistor, the gate layer 112′ of the gate electrode 200 is selectively oxidized, to form sidewall oxide 170, as illustrated in FIG. 3, where the portions of the gate electrode above the gate layer are collectively labeled 120. A sidewall oxide having a thickness of 50-70 angstroms is formed, for example, by exposing the gate stack to a mixture of hydrogen and oxygen (10% steam) at a temperature of 750° C. to selectively oxidize the poly relative to the tungsten and tungsten nitride. This selective oxidation of a gate stack is described in U.S. patent application Ser. No. 10/313,048 to Blosse et al. entitled “SELECTIVE OXIDATION OF GATE STACK” filed 6 Dec. 2002. After selective oxidation, additional processing is carried to complete formation of the semiconductor device, including implantation to form the source/drain regions in the semiconductor substrate, as well as annealing to activate the implanted ions in the source/drain regions and the gate layer. Typically, a single implant activation step is used for both the source/drain regions as well as the gate layer.